GAMMA: automating the HW mapping of DNN models on accelerators via genetic algorithm

DNN layers are multi-dimensional loops that can be ordered, tiled, and scheduled in myriad ways across space and time on DNN accelerators. Each of these choices is called a mapping. It has been shown that the mapping plays an extremely crucial role in overall performance and efficiency, as it direct...

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Bibliographic Details
Main Authors:	Kao, Sheng-Chun, Krishna, Tushar
Format:	Conference Proceeding
Language:	English
Subjects:	Computational modeling Computer architecture DNN accelerators DNN models domain-specific genetic algorithm GAMMA Genetic Algorithm genetic algorithms Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Hardware accelerators HW mapping ML accelerator multidimensional loops neural nets Optimization methods optimized mapping Parallel processing per-layer mappings Reconfigurable device search problems Space exploration Two dimensional displays
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