IJTAG Through a Two-Pin Chip Interface

IEEE 1687 (IJTAG) provides significant value to the DFT engineer and efficiency in the DFT flow. However, IJTAG requires 4 or 5 pins to drive an IEEE 1149.1 compliant TAP controller. Many of our designs have fewer than 4 pins total, prohibiting the usage of IJTAG. In this paper we describe a solutio...

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Bibliographic Details
Main Authors: Baby, Manu, Buttner, Bernd, Engelke, Piet, Pfannkuchen, Ulrike, Meier, Reinhard, Gaudet, Jonathan, Cote, J-F, Danialy, Givargis, Keim, Martin, Schramm, Lori
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Discrete Fourier transforms
Hardware
IEEE 1687
IEEE P1687.1
IJTAG
low pin-count
Pins
Protocols
Software
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Summary:IEEE 1687 (IJTAG) provides significant value to the DFT engineer and efficiency in the DFT flow. However, IJTAG requires 4 or 5 pins to drive an IEEE 1149.1 compliant TAP controller. Many of our designs have fewer than 4 pins total, prohibiting the usage of IJTAG. In this paper we describe a solution that drives an embedded TAP controller from a chip interface that consists of only 2 ports, a clock port and a bidirectional data port. The embedded TAP then drives the IJTAG network as usual, providing us all the benefits of IJTAG. To enable this, we needed to expand the used EDA tool's IJTAG support in the direction of IEEE P1687.1. Experiences from the implementation of this solution in a productive chip show significant productivity gains.
ISSN:2378-2250
DOI:10.1109/ITC44778.2020.9325232