Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique

This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple ope...

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Bibliographic Details
Published in:IEEE access 2021, Vol.9, p.28167-28176
Main Authors: Asif, Muhammad, Ali, Imran, Khan, Danial, Rehman, Muhammad Riaz Ur, Pu, Younggun, Yoo, Sang-Sun, Lee, Kang-Yoon
Format: Article
Language:English
Subjects:
Circuit design
Circuits
Clock generators
CMOS
Control systems
Current efficiency
Digital LDO
fast settling time
Feedback
hybrid type
low quiescent current
Metal oxide semiconductors
MOS devices
Power consumption
Power management
Regulators
Retention
Ripples
SSCG technique
Switches
Threshold voltage
Transistors
Voltage control
Voltage regulators
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Summary:This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple operation modes i.e. coarse, fine, and retention for high efficiency and transient enhancement. The proposed hybrid DF-LDO uses arrays of PMOS transistors in coarse and fine mode whereas in retention mode, only one comparator and NMOS are active and digital controller goes into the sleep mode. This results in the reduction of the power consumption and improves the output voltage ripples. In the retention mode, minimum number of blocks operate that reduces the current consumption as compared to coarse and fine modes. To further reduce the current consumption, the comparator with hysteresis is used. The proposed circuit is designed using CMOS 55 nm process. The input voltage range is from 0.8 ~ 1.5 V and the measured output voltage range is 0.756 ~ 1.456 V. The measured line regulation is 6 mV / V, and the regulation starts when the input voltage is 0.8 V. The measured load regulation is 2.3 mV/mA for maximum load current of 5 mA. The peak current efficiency of the proposed DF-LDO is 99.996 % with a maximum output voltage ripples value of 1.9 mV. The proposed digital LDO regulator active chip area is 0.012 mm 2 .
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3057225