An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation

This paper presents an energy-efficient deep neural network (DNN) training processor through the four key features: 1) Layer-wise Adaptive bit-Precision Scaling (LAPS) with 2) In-Out Slice Skipping (IOSS) core, 3) double-buffered Reconfigurable Accumulation Network (RAN), 4) momentum-ADAM unified OP...

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Bibliographic Details
Main Authors: Han, Donghyeon, Im, Dongseok, Park, Gwangtae, Kim, Youngwoo, Song, Seokchan, Lee, Juhyoung, Yoo, Hoi-Jun
Format: Conference Proceeding
Language:English
Subjects:
Adaptive systems
Benchmark testing
CMOS technology
Energy efficiency
Neural networks
Scalability
Training
Online Access:Request full text
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Summary:This paper presents an energy-efficient deep neural network (DNN) training processor through the four key features: 1) Layer-wise Adaptive bit-Precision Scaling (LAPS) with 2) In-Out Slice Skipping (IOSS) core, 3) double-buffered Reconfigurable Accumulation Network (RAN), 4) momentum-ADAM unified OPTimizer Core (OPTC). Thanks to the bit-slice-level scalability and zero-slice skipping, it shows 5.9 x higher energy-efficiency compared with the state-of-the-art on-chip-learning processor (OCLPs).
ISSN:2473-4683
DOI:10.1109/COOLCHIPS52128.2021.9410324