Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this articl...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-10, Vol.56 (10), p.2993-3007
Main Authors: Seol, Ji-Hwan, Choo, Kyojin, Blaauw, David, Sylvester, Dennis, Jang, Taekwang
Format: Article
Language:English
Subjects:
Bandwidth
Clocks
CMOS
Couplings
Digital controlled oscillator (DCO)
digital PLL
frequency synthesizer
Jitter
Oversampling
Phase locked loops
Phase noise
Power consumption
reference oversampling PLL (OSPLL)
reference spur
Vibration
Voltage-controlled oscillators
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