Electrical Performances of Fan-Out Embedded Bridge

• Main Authors: You, JinWei, Li, Jay, Ho, David, Li, Jackson, Zhuang, Ming Han, Lai, David, Chung, C. Key, Wang, Yu-Po
• Format: Conference Proceeding
• Language: English
• Subjects: Accelerator Wall; Artificial intelligence; Bridges; Computer architecture; Distance measurement; FO-EB; HIP; Packaging; Routing; Silicon; Space technology
• ISSN: 2377-5726
• DOI: 10.1109/ECTC32696.2021.00320

Artificial intelligent and interactive robotic engineering are evolving rapidly and shaping the new world in terms of medicine, machines, smart manufacturing and modern houses. To follow this trend, hyper-scaled data transmission is in demand. And the routing path out of memory-bank is the main index reflecting on computing performance at band-width transmission, data-rate latency, and power efficiency. Therefore high-bandwidth (HBW) memory was developed to enable this demand. But this HBW packages require 2/2\ \mu \mathrm{m} Cu line space to support such data efficiency. And they are packed together with GPU or ASIC dies to form a heterogeneous integrated package (HIP). The packaging can be either 2, 4, 6 or 8 HBWs. Thus, the architecture of this HIP is divided by three group: silicon dies, fan-out routing technology, organic interposer-selectively replaced by silicon bridge die. By reviewing HIP package in detail: First, silicon bridge interposer enhances the surface of three-dimension thermal dissipation and fabricates with the less than 1/1\ \mu \mathrm{m} line space technology while the fabrication cost of Through Si Via is too expensive. Second, fan-out routing technology is deploying the routing capability ranging from 2/2\ \mu \mathrm{m} to 10/10 um L/S outline profile as flexible power-ground connection platform to provide lower cost solution. However embedded die bridge technology has disadvantage of constraining scalability deployment for power and computation. This paper is to present the electrical metrics on Fan out embedded bridge module on substrate (FO-EB) at industrial benchmark by numerical analysis. The model renders the transporting performance of bit source deployed at high speed memory bank connection communicating through-hole-via routing at fan-out scalable area and reaching to another logic cell chip bank. The raised-module solution is the key to jump across the accelerator wall by advocating on bit-per-joule for next high performance computing.