Comparison of 3D Packages with 20 \mu \mathrm bump pitch using reflow soldering and thermal compression bonding

• Main Authors: Chan, Mu Hsuan, Chuang, Chris, Huang, Yu Lung, Chen, Wei Jhen, Jiang, Don Son, Huang, C.M., Chung, C. Key
• Format: Conference Proceeding
• Language: English
• Subjects: Advance package; Bonding; Chiplet integration; Chiplet stacking; Cu to Cu; Electronic packaging thermal management; Hybrid bond; intermetallic compound (IMC); Kirkendall void; Solder reflow; Stacking; Stress; TCB; Thermal conductivity; Three-dimensional displays; Transistors
• ISSN: 2377-5726
• DOI: 10.1109/ECTC32696.2021.00087

Moore's law has been slowed down in transistor scaling, but the demands of high computing processing does not cool down and the data rate transmission is growing exponentially in each day. The surge in high data rate causes present DDR4 memories succumb to this horrendous needs. High bandwidth memories (HBM) are then developed to fulfill these requirements. The upended trends drive up chiplets integrated package evolution. Presently most of these chiplets integrated packages are either homogeneously or heterogeneously packed together using 2.5D or Fan-Out-Multi-Chip Module. And these packages contain of micro bump pitches at the range of 40\sim 55 \mu \mathrm{m} . While HBM package are either stacked by 4 or 8 heights of memories dies with bump pitch of 40 \mu \mathrm{m} . Hybrid bond are then developed for much higher I/O density. However, hybrid bond technology has better economic values for bump pitch which is equal or below than 10 \mu \mathrm{m} . There is a grey area of bump pitch between 10\ \mu \mathrm{m} to 55\ \mu \mathrm{m} . Shall this package be assembled by hybrid bonding, reflow soldering, or thermal compression bonding (TCB)? The main challenges of this fine micro bump interconnections come with bump coplanarity, Kirkendall void formation and capillary underfill flow between the chip to chip spaces. This paper provides the answers to these challenges. A 3D package with 20 \mu \mathrm{m} bump pitch using chip to wafer stacking is developed. There are two test vehicles: TV 1 and TV 2 under the same conditions of 6.5^{\ast} 10.1\ \text{mm}^{2} in top chip, 10.1^{\ast} 11.1\ \text{mm}^{2} in bottom chip, < 50000 I/O count, and 13\ \mu \mathrm{m} (\text{diameter})/20\ \mu \mathrm{m} (pitch) bump. TV 1 uses solder reflow as stacking technology while TV 2 uses TCNCF (Thermal Compression Non Conductive Film.) Two types of bonding technologies are applied for comparison, which are solder reflow and thermal compression bonding (TCB). The test vehicle consists of 2 stacked chips, with die thickness of 70 \mu\mathrm{m} each. Top chip is first singulated and then placed on second chip at a wafer formed. Prior to the placement, the bump coplanarity is collected prior to placement. The chip-to-wafer bonding are then established by reflow soldering and TCB. Underfill is dispensed to the chip to chip gap is characterized. Optimized underfill materials are then applied to subsequent process. Followed by molding and grinding top chip to 70\ \mu \mathrm{m} thi