AFTAB: A RISC-V Implementation with Configurable Gateways for Security

• Main Authors: Rajabalipanah, Maryam, Roodsari, Mahboobe Sadeghipour, Jahanpeima, Zahra, Roascio, Gianluca, Prinetto, Paolo, Navabi, Zainalabedin
• Format: Conference Proceeding
• Language: English
• Subjects: Buffer Overflow; Computer architecture; Configurable Gateways; Embedded systems; Hardware; Hardware Implementation; Instruction sets; Logic gates; Processor; RISC-V; Security; Task analysis
• ISSN: 2472-761X
• DOI: 10.1109/EWDTS52692.2021.9580979

A processor plays an important role in the security of an entire embedded system. There are two reasons for this. One is that a processor is a general-purpose machine, the program of which can be altered for ill-intended purposes. The other factor that adds to the vulnerability of the embedded system is that an embedded processor uses memory addressing for all its instructions and data. This creates a wide-open gateway in and out of a processor by which secure data can be read, unintended data and instructions can be injected in the processor, and the processor can be made to perform unwanted tasks and operations. The remedy we have planned for this is securing the memory gateways and separating them from the rest of the processor architecture. This is to say that we design configurable gateways for instruction and data read and write operations that can be configured to prevent various forms of attacks coming from the processor's memory. These configurable gateway architectures are applied to a RISC-V architecture that we have implemented at the RT Level.This paper discusses our implementation of RISC-V architecture that we refer to as AFTAB. The paper emphasizes on the memory gateways of this processor and shows its interfaces with the configuration part of the processor and the architecture of the read and write gateways. After a general presentation of security and threads, we show how AFTAB gateways can be designed and configured for certain types of attacks. All works presented in this paper have been described at the RT Level and synthesized. The synthesis results will be presented.