Cu Clip-Bonding Method With Optimized Source Inductance for Current Balancing in Multichip SiC MOSFET Power Module

Cu clip-bonding is a promising packaging method for lower resistance, lower inductance, and higher reliability than wire-bonding. Previous studies only simply replace bond wires with Cu clips on an individual die. However, current sharing and thermal coupling issues among multichip modules are still...

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Bibliographic Details
Published in:IEEE transactions on power electronics 2022-07, Vol.37 (7), p.7952-7964
Main Authors: Wang, Laili, Zhang, Tongyu, Yang, Fengtao, Ma, Dingkun, Zhao, Cheng, Pei, Yunqing, Gan, Yongmei
Format: Article
Language:English
Subjects:
Bonding
Circuit design
Clips
Cu clip-bonding
Current sharing
Inductance
Layout
Logic gates
Mathematical analysis
Modules
MOSFET
MOSFETs
Multichip modules
Optimization
parasitic inductance
power module
Power sources
Silicon carbide
silicon carbide (SiC) <sc xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">mosfet
Temperature gradients
Thermal coupling
Wires
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Summary:Cu clip-bonding is a promising packaging method for lower resistance, lower inductance, and higher reliability than wire-bonding. Previous studies only simply replace bond wires with Cu clips on an individual die. However, current sharing and thermal coupling issues among multichip modules are still big challenges in the clip-bonded silicon carbide (SiC) mosfet power module. In this article, a novel source inductance optimization method is proposed. Extra modification paths (MPs) on Cu clips are used in this method. A clip-bonded half-bridge multichip SiC power module is designed and fabricated to verify the superiority of the method. In a simple straight layout, the distance between adjacent dies is large enough to avoid heat concentration and junction temperature differences resulting from the thermal coupling effect. The MPs structure on the Cu clip is designed to optimize the power source inductances. Parasitic circuit model and mathematical analysis are derived to demonstrate the features of proposed MPs. Simulations and experiments workbench are conducted to analyze drain current sharing performance. Derivation and simulation show the highest branch's inductance is reduced. Test results show the current imbalance and loss imbalance are relatively mitigated, which proves that the effect of power inductances imbalance is suppressed by the proposed optimization method.
ISSN:0885-8993
1941-0107
DOI:10.1109/TPEL.2022.3141373