PLMlight: Emulating Predictable Latency Mode in Regular SSDs

• Main Authors: Roy, Tanaya, Gupta, Jit, Kant, Krishna, Pal, Amitangshu, Minturn, Dave
• Format: Conference Proceeding
• Language: English
• Subjects: Access protocols; Estimation; Intel Optane; NVMe; Predictable Latency Mode (PLM); QoS; Quality of service; SSD; Tail Latency
• ISSN: 2643-7929
• DOI: 10.1109/NCA53618.2021.9685772

The interactive web applications increasingly demand an end-to-end latency that is not only low on the average but also is "deterministic" in that they avoid long tails. Storage systems today largely keep data in SSDs, but SSDs are known to have unpredictable latencies due to background activities such as garbage collection. The recent NVMe access protocol proposes a Predictable Latency Mode (PLM) which allows the SSD to cycle between deterministic window (DTWin) and nondeterministic window (NDWin) periods, with background activities largely pushed to the latter. However, this means that the number of read and write IOs during DTWin period is limited and need to be managed properly. Another challenge is that to date no real SSDs are available in the market with this feature. In this paper, we explore the possibility of emulating the PLM feature in regular SSDs using Intel Optane that does provide a rather deterministic access latency. In particular, we propose a write I/O friendly PLM light coordinator (PLMLC) that buffers writes in Optane and sends them to SSD during the NDWin-like period and also intelligently manages the limited number of IOs possible during DTWin-like period. The coordinator is designed to handle requests from multiple hosts that may access shared data on the SSD and may have different QoS requirements in terms of latencies. The results show that PLMLC improves the 99%-ile tail latency by 5.8x even without any sophisticated traffic estimation procedures.