A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrator...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2022-07, Vol.57 (7), p.2078-2089
Main Authors: Li, Hanyue, Shen, Yuting, Xin, Haoming, Cantatore, Eugenio, Harpe, Pieter
Format: Article
Language:English
Subjects:
Amplifiers
Analog to digital converters
Analog-digital conversion
Capacitors
Digital to analog converters
Duty-cycled amplifier
Energy consumption
high linearity
Integrators
loop filter
mismatch error shaping (MES)
Noise levels
Noise reduction
Noise shaping
noise-shaping successive-approximation-register (SAR) (NS-SAR) analog-to-digital converter (ADC)
Oversampling
Registers
Topology
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