A new hardware architecture for operations in GF(2/sup n/)

The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconv...

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Bibliographic Details
Published in:IEEE transactions on computers 2002-01, Vol.51 (1), p.90-92
Main Authors: Kim, Chang Han, Oh, Sangho, Lim, Jongin
Format: Article
Language:English
Subjects:
Architecture
Arithmetic
Computational efficiency
Hardware
Mathematical analysis
Multipliers
Optimization
Representations
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Summary:The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconventional basis and present a new bit-parallel multiplier which is as efficient as the modified Massey-Omura multiplier using the type I optimal normal basis.
ISSN:0018-9340
1557-9956
DOI:10.1109/12.980019