SABiNN: FPGA Implementation of Shift Accumulate Binary Neural Network Model for Real-Time Automatic Detection of Sleep Apnea

• Main Authors: Hassan, Omiya, Thakker, Rushil, Paul, Tanmoy, Parvin, Dilruba, Mohammad Mosa, Abu Saleh, Islam, Syed Kamrul
• Format: Conference Proceeding
• Language: English
• Subjects: Binarized Neural Network; Data models; Digital Hardware; Energy efficiency; Neural networks; Real-time systems; Shift-Accumulate; Sleep apnea; System-on-chip; Training
• ISSN: 2642-2077
• DOI: 10.1109/I2MTC48687.2022.9806534

This paper presents an energy-efficient digital hardware system design implemented on FPGA for real-time automatic detection of sleep apnea by embedding a proposed hardware model called Shift Accumulate Binary Neural Network (SABiNN). It is a three-hidden layer neural network model which was trained using sleep apnea data collected from PhysioNET bank consisting of 8 patient recordings of 8-10hrs of sleep periods. The data consisted of 2293 with apneic segments and 1522 with normal segments. For optimization and weight update, ADAM optimizer was employed, and the loss calculation was performed using Mean Squared Error (MSE) function. The best learned model parameters among multiple epochs were extracted, binarized and then fitted to the testing data set for further evaluation. The proposed design scheme yielded an accuracy of over 85% which is an acceptable rate in sleep diagnosis and screening. The proposed model inference on FPGA consumed power below 5 W which is significantly lower than that of the commercially available hardware accelerators for neural network applications. The proposed system design can be integrated onto a system-on-a-chip (SoC) platform to develop a smart wearable and automated sleep apnea detection device which is necessary for real-time critical health diagnosis and screening.