Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists

• Main Authors: Yamashita, Kazuki, Kato, Tomohiro, Hasegawa, Kento, Hidano, Seira, Fukushima, Kazuhide, Togawa, Nozomu
• Format: Conference Proceeding
• Language: English
• Subjects: adversarial attack; Circuit synthesis; Feature extraction; gate-level netlist; Hardware; hardware Trojan; machine learning; Manufacturing; neural network; Neural networks; Outsourcing; Robustness
• ISSN: 1942-9401
• DOI: 10.1109/IOLTS56730.2022.9897557

Recently, with the increase in outsourcing of IC design and manufacturing, the possibility of inserting hardware Trojans, which are circuits with malicious functions, has been pointed out. To prevent this threat, a method to identify hardware Trojans using neural networks has been proposed. On the other hand, adversarial attacks have emerged that modify circuit design information to reduce the accuracy of hardware-Trojan classification by neural networks. Since the features designed by existing methods do not take the attacks into account, it is necessary to consider a new method for countermeasures. In this paper, out of 76 features that are strongly related to hardware-Trojan features, we investigate them from the viewpoint of the robustness against the adversarial attacks on circuit design information and newly propose 24 hardware-Trojan features. We compare the classifiers using the proposed 24 features with the classifiers using 11, 36, 51, and 76 existing features, respectively and confirm that the proposed ones are more robust in identifying hardware Trojans in circuits subjected to the adversarial attacks.