Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

• Published in: IEEE transactions on electron devices 2022-11, Vol.69 (11), p.6095-6101
• Main Authors: Luo, Yanna, Cao, Lei, Zhang, Qingzhu, Cao, Yu, Zhang, Zhaohao, Yao, Jiaxin, Yan, Gangping, Zhang, Xuexiang, Gan, Weizhuo, Huo, Jiali, Xu, Haoqing, Tian, Guoliang, Bu, Weihai, Wu, Yongqin, Wu, Zhenhua, Yin, Huaxiang
• Format: Article
• Language: English
• Subjects: 6T static random-access memory (6T-SRAM) layout; CMOS; complementary FET (CFET); Computer architecture; Field effect transistors; Layout; Layouts; Microprocessors; Optimization; Parameter sensitivity; parasitic capacitance; parasitic resistance; Performance degradation; Performance evaluation; Rails; Resistance; Semiconductor devices; Sensitivity; Static random access memory; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3207972

Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( {R}_{\mathrm {pds}} , {R}_{\mathrm {pud}} ) and from access (AX) devices to bit-lines (BLs) ( {R}_{\mathrm{bax}} ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced {R}_{\mathrm{bax}} and increased {R}_{\mathrm {pud}} is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized {R}_{\mathrm{bax}} in the buried-BL scheme is proven to have higher WM, as well as lower WT. The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.