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Control of metamorphic buffer structure and device performance of InxGa1−xAs epitaxial layers fabricated by metal organic chemical vapor deposition

Using a step-graded (SG) buffer structure via metal-organic chemical vapor deposition, we demonstrate a high suitability of In0.5Ga0.5As epitaxial layers on a GaAs substrate for electronic device application. Taking advantage of the technique's precise control, we were able to increase the numb...

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Bibliographic Details
Published in:Nanotechnology 2014-12, Vol.25 (48)
Main Authors: Nguyen, H Q, Yu, H W, Luc, Q H, Tang, Y Z, Phan, V T H, Hsu, C H, Chang, E Y, Tseng, Y C
Format: Article
Language:English
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Summary:Using a step-graded (SG) buffer structure via metal-organic chemical vapor deposition, we demonstrate a high suitability of In0.5Ga0.5As epitaxial layers on a GaAs substrate for electronic device application. Taking advantage of the technique's precise control, we were able to increase the number of SG layers to achieve a fairly low dislocation density (∼106 cm−2), while keeping each individual SG layer slightly exceeding the critical thickness (∼80 nm) for strain relaxation. This met the demanded but contradictory requirements, and even offered excellent scalability by lowering the whole buffer structure down to 2.3 m. This scalability overwhelmingly excels the forefront studies. The effects of the SG misfit strain on the crystal quality and surface morphology of In0.5Ga0.5As epitaxial layers were carefully investigated, and were correlated to threading dislocation (TD) blocking mechanisms. From microstructural analyses, TDs can be blocked effectively through self-annihilation reactions, or hindered randomly by misfit dislocation mechanisms. Growth conditions for avoiding phase separation were also explored and identified. The buffer-improved, high-quality In0.5Ga0.5As epitaxial layers enabled a high-performance, metal-oxide-semiconductor capacitor on a GaAs substrate. The devices displayed remarkable capacitance-voltage responses with small frequency dispersion. A promising interface trap density of 3 × 1012 eV−1 cm−2 in a conductance test was also obtained. These electrical performances are competitive to those using lattice-coherent but pricey InGaAs InP systems.
ISSN:0957-4484
1361-6528
DOI:10.1088/0957-4484/25/48/485205