Crystalline In-Ga-Zn-O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating

• Published in: Japanese Journal of Applied Physics 2014-04, Vol.53 (4S), p.4-1-04EE12-6
• Main Authors: Kozuma, Munehiro, Okamoto, Yuki, Nakagawa, Takashi, Aoki, Takeshi, Ikeda, Masataka, Osada, Takeshi, Kurokawa, Yoshiyuki, Ikeda, Takayuki, Yamade, Naoto, Okazaki, Yutaka, Miyairi, Hidekazu, Fujita, Masahiro, Koyama, Jun, Yamazaki, Shunpei
• Format: Article
• Language: English
• Subjects: CMOS; Crystal structure; Field effect transistors; Field programmable gate arrays; Gate arrays; Gating and risering; Metal oxide semiconductors; Reduction; Switches
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/JJAP.53.04EE12

A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 µm c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 µm complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 µs at 2.5 V and 10 MHz driving.