Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

• Published in: Semiconductor science and technology 2010-04, Vol.25 (4), p.045014-045014
• Main Authors: Destefanis, V, Hartmann, J M, Huguenin, J L, Delaye, V, Samson, M P, Boulitreau, P, Morand, Y, Brianceau, P, Arvet, C, Gautier, P, Monfray, S, Skotnicki, T
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; Devices; Electronics; Etching; Exact sciences and technology; Gain; Mass flow; Microelectronic fabrication (materials and surfaces technology); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Silicon; Silicon germanides; Wafers
• ISSN: 0268-1242; 1361-6641
• DOI: 10.1088/0268-1242/25/4/045014

The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si0.7Ge0.3/Si stack. Given that SiGe(1 1 0) layers grown at 650 degree C in windows of patterned wafers are rough, we have first of all studied the 600 degree C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 degree C down to 600 degree C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH4)/F(SiH2Cl2) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 degree C and 725 degree C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 degree C on (1 0 0) or at 600 degree C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5--3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were notably obtained for the lateral etching of the (1 1 0) and (1 0 0) SiGe sacrificial layers (thanks to a CF4-based dry plasma), with no anisotropy. Significant hole mobility gains (electron mobility loss) compared to the universal Si(1 0 0)/SiO2 mobility were evidenced in long, narrow (L = 10 mu m; W = 0.08 mu m) 'bulk-like' epitaxial Si(1 1 0) L-SOI devices (i.e. with SiGe still present under most of the Si channel). The gain (the loss) monotonically increased from 120% (11%) up to 246% (58%) when moving away from the [0 0 1] direction toward the [1 -1