The design of microsupercomputers

As supercomputer performance continues to grow, packaging techniques will remain critical for reducing chip-to-chip delays. In addition, higher integration levels will become increasingly important because they can drastically reduce the number of chip crossings. Microcomputer systems have enjoyed a...

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 1991-01, Vol.24:1
Main Authors: Mudge, T.N., Brown, R.B., Birmingham, W.B., Dykstra, J.A., Kayssi, A.I., Lomax, R.J., Olukotun, O.A., Sakallah, K.A., Milano, R.A.
Format: Article
Language:English
Subjects:
426002 - Engineering- Lasers & Masers- (1990-)
990200 - Mathematics & Computers
COMPUTER ARCHITECTURE
COMPUTER CODES
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
ENGINEERING
FIELD EFFECT TRANSISTORS
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MEMORY MANAGEMENT
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
PROGRAMMING LANGUAGES
SEMICONDUCTOR DEVICES
SUPERCOMPUTERS
TRANSISTORS
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Summary:As supercomputer performance continues to grow, packaging techniques will remain critical for reducing chip-to-chip delays. In addition, higher integration levels will become increasingly important because they can drastically reduce the number of chip crossings. Microcomputer systems have enjoyed a performance increase of 100 to 200 percent every three years, in large part due to the growth in chip integration density. In contrast, mainframe supercomputers have improved by only about 50 percent every three years. It should not be surprising then, if the next generation of supercomputers evolves from the microprocessor rather than continuing the mainframe tradition. This article describes the author's work to develop a prototype microsupercomputer. It does so by using GaAs Mesfet E/D DCFL (gallium arsenide, metal semiconductor field effect transistor, enhancement/depletion direct-coupled FET logic) a high-speed technology that has good integration density, and by using state-of-the-art packaging technology to prevent chip crossings from dominating the overall speed of the system.
ISSN:0018-9162
1558-0814
DOI:10.1109/2.67194