Memory access dependencies in shared-memory multiprocessors

The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency m...

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Bibliographic Details
Published in:IEEE transactions on software engineering 1990-06, Vol.16 (6), p.660-673
Main Authors: Dubois, M., Scheurich, C.
Format: Article
Language:English
Subjects:
990200 - Mathematics & Computers
Algorithms
Applied sciences
Architecture
ARRAY PROCESSORS
Bakeries
Cache
Coherence
Communication
COMPUTER ARCHITECTURE
Computer science
control theory
systems
Computer systems and distributed systems. User interface
COMPUTERIZED SIMULATION
Concurrent computing
Design
Exact sciences and technology
Gallium arsenide
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
Hardware
Implementations
Information processing
Memory
MEMORY MANAGEMENT
Methods
Microprocessors
Multiprocessing
Multiprocessing systems
Parallel algorithms
PARALLEL PROCESSING
Pipeline processing
Program processors
PROGRAMMING
SIMULATION
Software
Supercomputers
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Description
Summary:The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures.< >
ISSN:0098-5589
1939-3520
DOI:10.1109/32.55094