Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model

This paper validates an integrated yield-reliability model for redundant memory using yield and stress test data from a 36 Mbit SRAM memory chip and an 8 Mbit embedded DRAM chip. In both cases, those chips determined functional following wafer test and repair were subjected to voltage stress and bur...

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Bibliographic Details
Main Authors: Barnett, T.S., Grady, M., Purdy, K., Singh, A.D.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Circuit testing
Design. Technologies. Operation analysis. Testing
Electronics
Embedded computing
Exact sciences and technology
Integrated circuit modeling
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic testing
Microelectronics
Occupational stress
Predictive models
Redundancy
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Testing, measurement, noise and reliability
Voltage
Online Access:Request full text
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Summary:This paper validates an integrated yield-reliability model for redundant memory using yield and stress test data from a 36 Mbit SRAM memory chip and an 8 Mbit embedded DRAM chip. In both cases, those chips determined functional following wafer test and repair were subjected to voltage stress and burn-in. It is shown that the yield-reliability model can accurately model not only the fraction of die with 0, 1, 2, ... repairs, but also predict the number of stress test failures for a die with a given number of repairs. Because defects in integrated circuits tend to cluster, it has been suspected that repaired die have a greater chance of containing early-life reliability defects than die with no repairs. Repaired die should therefore be more likely to fail stress tests than die with no repairs. This work presents the first experimental validation of these statements. In particular, experimental results indicate that, as predicted by the yield-reliability model, the stress test failure probability is linearly related to the number of repairs; the slope of this line is intimately related to the degree to which defects cluster over the wafer. Model predictions are in excellent agreement with observed data.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2002.1041821