Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

• Main Authors: Seung Wook Yoon, Kripesh, V., Li Hong Yu, Li Chao Yong, Su Yong Ji Jeffrey, Iyer, M.K.
• Format: Conference Proceeding
• Language: English
• Subjects: Adhesives; Applied sciences; Copper; Design. Technologies. Operation analysis. Testing; Dielectric devices; Dielectric materials; Electronics; Electronics industry; Exact sciences and technology; Failure analysis; General (including economical and industrial fields); Integrated circuit interconnections; Integrated circuits; Metallization; Moore's Law; Semiconductor device packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability; Transistors
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2004.1320334

As CMOS transistor scaling proceeds into the deep submicron regime, the number of transistors on high performance, high density ICs is increasing to 45/spl sim/60 millions, in accordance with the historical trend of Moore's Law. It is the fundamental motivating factor causing the semiconductor industry to move away from aluminum as interconnect metal with silicon dioxide dielectric between the metal lines, to copper metal and ultra-low-k dielectric materials. Copper reduces the resistance of the metal interconnect lines, while low-k dielectrics reduce the parasitic capacitance between the metal lines: The implementation of copper as an interconnect in conjunction with the ultra low-k materials as interlevel dielectrics (ILDs) or intermetal dielectrics (IMDs) in the fabrication of ULSI circuits has been a main stream especially for high speed devices in the semiconductor community worldwide. The impact of UBM integrity in Cu metallization has been reported and major failure mechanism observed were metal peeling from low-k dielectrics. However investigations reported with different chip ILD/IMD stacking structure and with various UBM metallization and failure analysis of the same particularly with ultra low-k dielectrics are very limited. In this work, two different approaches are studied. One is for chip-side stack structure and another is the application of wafer level packaging technology. The bump failure is found at the chip-side, especially, at the interface of ultra low-k dielectrics materials. To increase the bump adhesion properties, different thickness ILDs were deposited and various adhesion promoter layers were evaluated with several stack structures. In order to achieve the proper solder joint reliability in other approach, wafer level integration techniques were applied. Encapsulation of photosensitive low-k dielectrics and BCB (Benzocyclobutene) were carried out on the Cu/ultra-low-k dielectric wafers. According to the characterization, it gave promising results in view point of adhesion, thus, no more chip-side failure is found. The process, assembly steps, test vehicle design and reliability results, failures and analysis will be reported.