A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2010-04, Vol.18 (4), p.662-666
• Main Authors: Kao, Chao-Yang, Wu, Cheng-Long, Lin, Youn-Long
• Format: Article
• Language: English
• Subjects: Acceleration; Architecture; Automatic voltage control; Coding; Computation; Computational complexity; Computational efficiency; Computer architecture; Electronics industry; Engines; Gates; H.264/AVC; Hardware; Motion estimation; Parallel processing; Semiconductors; Very large scale integration; Video coding; VLSI architecture
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2013629

Variable-block-size motion estimation (VBSME) is one of the contributors to H.264/Advanced Video Coding (AVC)'s excellent coding efficiency. Due to its high computational complexity, however, VBSME needs acceleration for real-time high-resolution applications. We propose a high-performance hardware architecture for H.264/AVC fractional motion estimation. Our architecture consists of three parallel processing engines, one for 4 × 4 and 8 × 8 blocks, one for 8 × 4 and 4 × 8 blocks, and another for the remaining type of blocks. In addition, we propose a resource-sharing scheme which saves 33% of hardware cost for the computation of the sum of absolute transformed difference. Synthesized into a Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm CMOS cell library, our 321-K gate design only needs to run at 154 MHz when encoding a 1920 ×1088 video at 30 frames per second. Compared with a most comparable previous work that consumes 311 K gates and runs at 200 MHz, our proposed architecture is more efficient.