Domain-Specific Many-core Computing using Spin-based Memory

• Published in: IEEE transactions on nanotechnology 2014-09, Vol.13 (5), p.881-894
• Main Authors: Venkatesan, Rangharajan, Chippa, Vinay K., Augustine, Charles, Roy, Kaushik, Raghunathan, Anand
• Format: Article
• Language: English
• Subjects: Algorithms; Architecture; Computation; Computer architecture; Context; Devices; Domain-specific computing; Magnetic tunneling; Magnetization; many-core processor; Microprocessors; Phase change random access memory; Platforms; Random access memory; Semiconductors; spin-based memory; System-on-chip; Vector quantization
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2014.2306958

Spin-based devices have shown great potential in enabling high-density, energy-efficient memory and are therefore, considered highly promising for the design of future computing platforms. While the impact of spin-based devices on general-purpose computing platforms has been studied, they are yet to be explored in the context of domain-specific computing, where the characteristics of the devices can be matched to application characteristics through architectural customization, so as to maximize the benefits. We present the design and evaluation of a many-core domain-specific processor for the emerging application domains of Recognition and Mining (RM) using spin-based memories. The domain-specific processor has a two-level on-chip memory hierarchy consisting of a streaming access first-level memory and a random access second-level memory. Based on the memory access characteristics, we suggest the use of Domain Wall Memory (DWM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) to realize the first and second levels, respectively. We develop architectural models of DWM and STT-MRAM, and use them to evaluate the proposed design and explore various architectural tradeoffs in the domain-specific processor. We evaluate the proposed design by comparing it to a CMOS-based baseline at the same technology node. For three representative RM algorithms (support vector machine, k-means clustering, and generalized learning vector quantization), the spin-memory-based design achieves an energy-delay product improvement of 1.5 ×-4 × over the CMOS baseline at iso-area. Our results suggest that spin-based memory technologies can enable significant improvements in energy efficiency and performance for highly parallel, data-intensive workloads. Our study also highlights the importance of synergistic architectural exploration along with the use of emerging devices rather than simply considering them as drop-in replacements.