Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

• Published in: IEEE transactions on electron devices 2015-01, Vol.62 (1), p.213-219
• Main Authors: Fan, Jiewen, Li, Ming, Xu, Xiaoyan, Yang, Yuancheng, Xuan, Haoran, Huang, Ru
• Format: Article
• Language: English
• Subjects: Band-to-band tunneling (BTBT); CMOS technology; Doping; gate-induced drain leakage (GIDL); Junctions; Logic gates; Optimization; power consumption; Shape; Silicon; silicon nanowire transistors (SNWTs); Tunneling
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2014.2371916

In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter (D nw ) devices under low IV gs I. It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices. On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high IV gs I with relatively large D nw . Systematic study of GIDL dependence on process parameters, including D nw cross-sectional shape, doping, and overlap length (L ov ), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing D nw and L ov despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.