Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2015-10, Vol.23 (10), p.2001-2008
• Main Authors: Bhattacharyya, Partha, Kundu, Bijoy, Ghosh, Sovan, Kumar, Vinay, Dandapat, Anup
• Format: Article
• Language: English
• Subjects: Adders; Capacitance; Carry propagation adder; CMOS; Delays; Design engineering; high speed; hybrid design; Logic gates; low power; Power demand; Propagation delay; Transistors
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2357057

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 μW) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 μW and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79-μW (53.36-μW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.