A Sub-GHz Wireless Transmitter Utilizing a Multi-Class-Linearized PA and Time-Domain Wideband-Auto I/Q-LOFT Calibration for IEEE 802.11af WLAN

• Published in: IEEE transactions on microwave theory and techniques 2015-10, Vol.63 (10), p.3228-3241
• Main Authors: Ka-Fai Un, Wei-Han Yu, Chak-Fong Cheang, Gengzhen Qi, Pui-In Mak, Martins, Rui P.
• Format: Article
• Language: English
• Subjects: Adjacent channel leakage ratio (ACLR); Calibration; CMOS; digital calibration; Efficiency; G_{ m}-C low-pass filter; Gain; Harmonic analysis; harmonic rejection mixer (HRM); harmonic rejection ratio (HRR); IEEE 802.11af; image rejection ratio (IRR); in-phase/quadrature (I/Q) imbalance; Linearity; LO feedthrough (LOFT); LO-leakage rejection ratio (LRR); local oscillator (LO); power amplifier (PA); Power generation; Transconductance; transmitter (TX); Wideband
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2015.2462815

Broadband dynamic spectrum access in the sub-GHz band emerges as a potential solution for deploying low-cost range-enhanced wireless connectivity, suitable for under/less-developed countries. This paper describes a sub-GHz wireless transmitter (TX) with an integrated multi-class-linearized power amplifier (PA) compliant with the IEEE 802.11af wireless local-area network. It features a wideband in-phase/quadrature (I/Q) modulator exploiting two-stage 6-/14-path harmonic-rejection mixers plus G m- C low-pass filters to manage the spurs emission induced by hard-switched mixing. The entailed 8/16-phase local oscillator (LO) is generated by injection-locked phase correctors plus frequency dividers to relax the frequency and tuning range of the reference LO. The linearized PA features overdriven-class-A/B/C cells to balance the power efficiency and linearity; a dual-gate input pair to enlarge the linear gain range; and a wideband low-impedance ground at the second harmonic to suppress the harmonic distortion and ground bounces. The wideband I/Q imbalance and LO feedthrough are resolved by automatic digital calibration, which incorporates time-domain parameter estimation for better computational efficiency. Benchmarking with the recent art, this TX + PA solution fabricated in 65-nm CMOS exhibits higher system power efficiency (from 7.4% to 18.5%) and 1-dB compression point (from OP1 dB: + 12.5 to + 16.3 dBm). When delivering a 64-QAM orthogonal frequency division multiplexing signal at > + 10 dBm, the chip demonstrates sufficiently low noise floor ( -143 dBc/Hz), adjacent channel leakage ratio ( dB), and error vector magnitude fulfilling the specifications.