A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large s...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2017-08, Vol.52 (8), p.2194-2207
Main Authors: Lee, Albert, Chieh-Pu Lo, Chien-Chen Lin, Wei-Hao Chen, Kuo-Hsiang Hsu, Zhibo Wang, Fang Su, Zhe Yuan, Qi Wei, Ya-Chin King, Chrong-Jung Lin, Hochul Lee, Amiri, Pedram Khalili, Kang-Lung Wang, Yu Wang, Huazhong Yang, Yongpan Liu, Meng-Fan Chang
Format: Article
Language:English
Subjects:
CMOS
Computing time
Energy storage
Flip-flop (FF)
Flip-flops
Latches
Memory devices
Microprocessors
nonvolatile logic
Nonvolatile memory
nonvolatile processor (nv-Processor)
Processors
Program processors
Random access memory
Reliability
Resistive RAM
resistive RAM (ReRAM)
Response time
Stress concentration
Switches
Switching
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Summary:Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy (ES) and long voltage stress time on the device (TSTRESS), due to wide distribution in the write time of NVM device as well as unnecessary writes. Moreover, heavy parasitic load on the power rail cause long wake-up time for restoring data from NVM to FFs. This paper proposes the resistive RAM (ReRAM)-based nvFF with self-write termination (SWT) and reduced loading on power rail to: 1) reduce 93+% waste of ES from fast switching or matched cells; 2) suppress endurance and reliability degradation resulted from overprogramming and long TSTRESS; and 3) achieve reliable and 26+ times faster restore operation compared with previous nvFFs. We have fabricated a nonvolatile processor and a test chip with SWT-nvFFs using logic-process ReRAM in a 65-nm CMOS process. Measured results show sub-2-ns termination response time and sub-20-ns chip-level restore time.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2700788