Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

Deep convolutional neural networks (DCNNs) have been successfully used in many computer vision tasks. Previous works on DCNN acceleration usually use a fixed computation pattern for diverse DCNN models, leading to imbalance between power efficiency and performance. We solve this problem by designing...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2017-08, Vol.25 (8), p.2220-2233
Main Authors: Tu, Fengbin, Yin, Shouyi, Ouyang, Peng, Tang, Shibin, Liu, Leibo, Wei, Shaojun
Format: Article
Language:English
Subjects:
Acceleration
Artificial neural networks
Computation
Computation pattern
Computational modeling
Computer architecture
Computer vision
Convolution
Data paths
deep convolutional neural networks (DCNNs)
Deoxyribonucleic acid
DNA
Efficiency
Energy consumption
Kernel
Mapping
Mathematical models
neural network accelerator
Neural networks
Power consumption
Power efficiency
Random access memory
reconfigurable architecture
Reuse
Scheduling
scheduling framework
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Summary:Deep convolutional neural networks (DCNNs) have been successfully used in many computer vision tasks. Previous works on DCNN acceleration usually use a fixed computation pattern for diverse DCNN models, leading to imbalance between power efficiency and performance. We solve this problem by designing a DCNN acceleration architecture called deep neural architecture (DNA), with reconfigurable computation patterns for different models. The computation pattern comprises a data reuse pattern and a convolution mapping method. For massive and different layer sizes, DNA reconfigures its data paths to support a hybrid data reuse pattern, which reduces total energy consumption by 5.9~8.4 times over conventional methods. For various convolution parameters, DNA reconfigures its computing resources to support a highly scalable convolution mapping method, which obtains 93% computing resource utilization on modern DCNNs. Finally, a layer-based scheduling framework is proposed to balance DNA's power efficiency and performance for different DCNNs. DNA is implemented in the area of 16 mm 2 at 65 nm. On the benchmarks, it achieves 194.4 GOPS at 200 MHz and consumes only 479 mW. The system-level power efficiency is 152.9 GOPS/W (considering DRAM access power), which outperforms the state-of-the-art designs by one to two orders.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2017.2688340