Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positi...

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Bibliographic Details
Published in:IEEE electron device letters 2018-01, Vol.39 (1), p.8-11
Main Authors: Lin, Jer-Yi, Kumar, Malkundi Puttaveerappa Vijay, Chao, Tien-Sheng
Format: Article
Language:English
Subjects:
Bias
Degradation
Integrated circuits
inversion mode (IM)
Junctionless (JL)
Logic gates
Nanoscale devices
nanosheet
Nanosheets
Object recognition
positive gate bias stress (PGBS)
Reliability
Semiconductor devices
Stress
Stresses
Thin film transistors
thin-film transistor (TFT)
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Summary:In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2017.2779451