A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks

• Published in: IEEE journal of solid-state circuits 2018-01, Vol.53 (1), p.66-75
• Main Authors: Price, Michael, Glass, James, Chandrakasan, Anantha P.
• Format: Article
• Language: English
• Subjects: Acoustics; Artificial neural networks; Automatic speech recognition; Bandwidth; CMOS digital integrated circuits; Computer architecture; deep neural networks (DNNs); Hidden Markov models; Integrated circuit modeling; Microprocessors; Neural networks; Power consumption; Speech; Speech recognition; voice activity detection (VAD); Voice activity detectors; Voice recognition; weighted finite-state transducers (WFSTs)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2752838

This paper describes digital circuit architectures for automatic speech recognition (ASR) and voice activity detection (VAD) with improved accuracy, programmability, and scalability. Our ASR architecture is designed to minimize off-chip memory bandwidth, which is the main driver of system power consumption. A SIMD processor with 32 parallel execution units efficiently evaluates feed-forward deep neural networks (NNs) for ASR, limiting memory usage with a sparse quantized weight matrix format. We argue that VADs should prioritize accuracy over area and power, and introduce a VAD circuit that uses an NN to classify modulation frequency features with 22.3-μW power consumption. The 65-nm test chip is shown to perform a variety of ASR tasks in real time, with vocabularies ranging from 11 words to 145000 words and full-chip power consumption ranging from 172 μW to 7.78 mW.