A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC

Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Alt...

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Bibliographic Details
Published in:The Journal of supercomputing 2018-02, Vol.74 (2), p.665-695
Main Authors: Siddique, Nafiul A., Grubel, Patricia A., Badawy, Abdel-Hameed A., Cook, Jeanine
Format: Article
Language:English
Subjects:
Benchmarks
Business metrics
Compilers
Computer memory
Computer Science
Evictions
Interpreters
Microprocessors
Performance measurement
Processor Architectures
Programming Languages
Utilization
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Summary:Cache has long been used to minimize the latency of main memory accesses by storing frequently used data near the processor. Processor performance depends on the underlying cache performance. Therefore, significant research has been done to identify the most crucial metrics of cache performance. Although the majority of research focuses on measuring cache hit rates and data movement as the primary cache performance metrics, cache utilization is significantly important. We investigate the application’s locality using cache utilization metrics. Furthermore, we present cache utilization and traditional cache performance metrics as the program progresses providing detailed insights into the dynamic application behavior on parallel applications from four benchmark suites running on multiple cores. We explore cache utilization for APEX, Mantevo, NAS, and PARSEC, mostly scientific benchmark suites. Our results indicate that 40% of the data bytes in a cache line are accessed at least once before line eviction. Also, on average a byte is accessed two times before the cache line is evicted for these applications. Moreover, we present runtime cache utilization , as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. To facilitate this research, we build a memory simulator incorporated into the Structural Simulation Toolkit (Rodrigues et al. in SIGMETRICS Perform Eval Rev 38(4):37–42, 2011 ). Our results suggest that variable cache line size can result in better performance and can also conserve power.
ISSN:0920-8542
1573-0484
DOI:10.1007/s11227-017-2144-1