Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals

• Published in: IEEE journal of solid-state circuits 2018-04, Vol.53 (4), p.1102-1114
• Main Authors: Park, Sung-Yun, Cho, Jihyun, Lee, Kyuseok, Yoon, Euisik
• Format: Article
• Language: English
• Subjects: Analog circuits; Analog to digital conversion; Analog to digital converters; Bandwidth; Broadband communication; CMOS; Correlation; Data transmission; Dynamic power; Entropy (Information theory); extracellular action potential (EAP or spike); high-density neural recording; local field potential (LFP); lossless compression; modular; Neurons; neuroscience; Power consumption; Power demand; Probes; Recording; Reduction; Redundancy; scalable; Signal paths; spatiotemporal correlation; Spatiotemporal phenomena; Spikes; System effectiveness; temporal sparsity; Waveforms
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2787749

We report a scalable neural recording interface with embedded lossless compression to reduce dynamic power consumption ( \text{P}_{D} ) for data transmission in high-density neural recording systems. We investigated the characteristics of neural signals and implemented effective lossless compression for local field potential (LFP) and extracellular action potential (EAP or spike) in separate signal paths. For LFP, spatial-temporal (spatiotemporal) correlation of the LFP signals is exploited in a \Delta -modulated \Delta \Sigma analog-to-digital converter ( \Delta -\Delta \Sigma ADC) and a dedicated digital difference circuit. Then, statistical redundancy is further eliminated through entropy encoding without information loss. For spikes, only essential parts of waveforms in the spikes are extracted from the raw data by using spike detectors and reconfigurable analog memories. The prototype chip was fabricated using 180-nm CMOS processes, incorporating 128 channels into a modular architecture that is easily scalable and expandable for high-density neural recordings. The fabricated chip achieved the data rate reduction for the LFPs and spikes by a factor of 5.35 and 10.54, respectively, from the proposed compression scheme. Consequently, P_{D} was reduced by 89%, when compared to the uncompressed case. We also achieved the state-of-the-art recording performance of 3.37 \mu \text{W} per channel, 5.18 \mu V_{\mathrm {rms}} noise, and 3.41 {\text {NEF}}^{2}V_{\mathrm {DD}} .