A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception

Implementing neuromorphic algorithms is increasingly interesting as the error resilience and low-area, low-energy nature of biological systems becomes the potential solution for problems in robotics and artificial intelligence. While conventional digital methods are inefficient in implementing massi...

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Bibliographic Details
Published in:Journal of signal processing systems 2018-05, Vol.90 (5), p.709-725
Main Authors: Boga, Kaushik, Leduc-Primeau, François, Onizawa, Naoya, Matsumiya, Kazumichi, Hanyu, Takahiro, Gross, Warren J.
Format: Article
Language:English
Subjects:
Binocular vision
Circuits and Systems
CMOS
Computer Imaging
Electrical Engineering
Energy
Energy consumption
Engineering
Floating point arithmetic
Floating structures
Image Processing and Computer Vision
Integrated circuits
Multilayers
Neural networks
Pattern Recognition
Pattern Recognition and Graphics
Signal,Image and Speech Processing
Space perception
Structural hierarchy
Very large scale integration
Vision
Vision systems
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Summary:Implementing neuromorphic algorithms is increasingly interesting as the error resilience and low-area, low-energy nature of biological systems becomes the potential solution for problems in robotics and artificial intelligence. While conventional digital methods are inefficient in implementing massively parallel systems, analog solutions are hard to design and program. Stochastic Computing (SC) is a natural bridge that allows pseudo-analog computations in the digital domain using low complexity hardware. However, large scale SC systems traditionally suffered from long latencies, hence higher energy consumption. This work develops a VLSI architecture for an SC based binocular vision system based on a disparity-energy model that emulates the hierarchical multi-layered neural structure in the primary visual cortex. The 3-layer neural network architecture is biologically plausible and is tuned to detecting 5 different disparities. The architecture is compact, adder-free, and achieves better disparity detection compared to a floating-point version by using a modified disparity-energy model. A generalized 1x100 pixel processing system is synthesized using TSMC 65nm CMOS technology and it achieves 71 % reduction in area-delay product and 48 % in energy savings compared to a fixed-point implementation at equivalent precision.
ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-016-1197-3