Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors

• Published in: arXiv.org 2012-03
• Main Authors: Prati, Enrico, De Michielis, Marco, Belli, Matteo, Cocco, Simone, Fanciulli, Marco, Kotekar-Patil, Dharmraj, Ruoff, Matthias, Kern, Dieter P, Wharam, David A, Verduijn, Arjan, Tettamanzi, Giuseppe, Rogge, Sven, Roche, Benoit, Wacquez, Romain, Jehl, Xavier, Vinet, Maud, Sanquer, Marc
• Format: Article
• Language: English
• Subjects: CMOS; Density functional theory; Electron beam lithography; Electron transport; Electrons; Metal oxide semiconductors; Metal oxides; N-type semiconductors; Nanoelectronics; Quantum dots; Semiconductor devices; Silicon; Single-electron transistors; Transistors
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.1203.4811

We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 \(\times\) 20 nm\(^{2}\) is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices.