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Variability‐aware design of a bandgap voltage reference with 0.18% standard deviation and 68 nW power consumption
Summary In this paper, we present a design approach based on a reassessment of design priorities to obtain robust circuits with respect to process variability. We show that if we address variability as one of the main issues in circuit design, and make it inform our very first design choices, we are...
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Published in: | International journal of circuit theory and applications 2018-11, Vol.46 (11), p.1985-1999 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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In this paper, we present a design approach based on a reassessment of design priorities to obtain robust circuits with respect to process variability. We show that if we address variability as one of the main issues in circuit design, and make it inform our very first design choices, we are able to significantly reduce dispersion of circuit characteristics without degrading of the other performance figures. We apply this variability‐aware approach to the design of a nanopower reference voltage generator in 0.18‐μm CMOS technology. The result is a BJT‐based topology, which provides a reference voltage of about 241 mV from a 1 V supply voltage. Measurements on 20 samples from a single batch show that the reference voltage exhibits a relative standard deviation of 0.18%, while consuming only 68.3 nW. This is comparable with the performance of references that are either trimmed or consume much more power. This reduced process sensitivity comes at the cost of a significant increase of die area (0.28 mm2).
The paper presents a nanopower process‐stable voltage reference, based on a current summing approach. The circuit exhibits an unprecedented stability of the reference voltage (241 mV) with respect to process variations (σ/μ = 0.18%) associated with an extreme low power consumption (68 nW). After an in‐depth discussion of the strategies used to minimize the effect of process variations to the output voltage, extensive corroborating experimental data are presented, which includes measurements obtained from 3 batches of 20 samples. |
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ISSN: | 0098-9886 1097-007X |
DOI: | 10.1002/cta.2510 |