Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes,...

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Bibliographic Details
Published in:International journal of parallel programming 2018-12, Vol.46 (6), p.1220-1246
Main Authors: Kyrkou, Christos, Theocharides, Theocharis, Bouganis, Christos-Savvas, Polycarpou, Marios
Format: Article
Language:English
Subjects:
Classification
Computer architecture
Computer Science
Field programmable gate arrays
Frames per second
Hardware
Image classification
Image detection
Image processing
Object recognition
Processor Architectures
Reduction
Software Engineering/Programming and Operating Systems
State of the art
Support vector machines
Theory of Computation
Video
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Summary:Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on 800 × 600 resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by ∼ 30%, and simultaneously observed ∼ 20% peak power reduction compared to a baseline implementation.
ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-017-0514-1