Thorough Understanding of Retention Time of Z2FET Memory Operation

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. I...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2019-01, Vol.66 (1), p.383-388
Main Authors: Duan, M., Navarro, C., Cheng, B., Adamu-Lema, F., Wang, X., Georgiev, V. P., Gamiz, F., Millar, C., Asenov, A.
Format: Article
Language:English
Subjects:
Accumulation
Cathodes
Computer memory
Degradation
Dynamic random access memory
Dynamic random access memory (DRAM)
Electric potential
Electron traps
Electrons
generation
injection
Ionization
Logic gates
Memory management
Potential barriers
Random access memory
recombination
Retention
retention time
Shockley–Read–Hall (SRH)
Switches
TCAD
transistor
volatile memory
Z2FET
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Summary:A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD "0" retention time originates from the gated-silicon on insulator (SOI) portion rather than the intrinsic-SOI region of the Z2FET. Electrons accumulate under front gate and finally collapse the potential barrier turning logic "0"-"1." It appears that Shockley-Read-Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. The results show that the downscaling of Lg has little effect on data "0" retention, but Lin is limited to ~125 nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75 nm. We have demonstrated by 2-D TCAD simulation that Z2FET is a promising DRAM cells' candidate particularly for Internet-of-Things applications.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2018.2877977