Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

• Published in: Multimedia tools and applications 2019-07, Vol.78 (13), p.18309-18338
• Main Authors: Shet, K. Sathish, Aswath, A. R., Hanumantharaju, M. C., Gao, Xiao-Zhi
• Format: Article
• Language: English
• Subjects: Access control; Algorithms; Computer Communication Networks; Computer Science; Data Structures and Information Theory; Embedded systems; Embedding; Field programmable gate arrays; High speed; Image resolution; Multimedia Information Systems; Pixels; Reconfiguration; Special Purpose and Application-Based Systems; Steganography
• ISSN: 1380-7501; 1573-7721
• DOI: 10.1007/s11042-019-7187-2

Exploiting modification direction (EMD)-based image steganography algorithm has higher embedding efficiency, low distortion, and best security that finds application in secure communication, data protection, access control in digital content distribution, etc., EMD steganography encapsulates secret digit represented in (2n + 1)-ary notational system by increasing or decreasing one of the n cover pixels by one. New high-speed reconfigurable architectures and field programmable gate array (FPGA) implementation of EMD based image steganography algorithms have been proposed. Although, earlier work on FPGA implementation of steganography algorithms offer higher speed, low chip area, and better throughput it usually operates on a fixed number of pixels. The proposed system works well for both arbitrary numbers of pixel groups and variable image resolution. The developed system is capable of embedding a secret message from two to eight-pixel groups with an image resolution of 512 × 512 pixels at a real-time video rate of 549 frames/s.. The complete design is implemented using RTL compliant Verilog code which fits into a single FPGA/ASIC chip with a gate density of two million gates.