A Productivity-Oriented Wafer Map Optimization Using Yield Model Based on Machine Learning

• Published in: IEEE transactions on semiconductor manufacturing 2019-02, Vol.32 (1), p.39-47
• Main Authors: Kim, Jong-Seong, Jang, Sung-Ju, Kim, Tae-Woo, Lee, Hyun-Jin, Lee, Jong-Bae
• Format: Article
• Language: English
• Subjects: Artificial neural networks; Business competition; Fabrication; Integrated circuits; Lithography; Machine learning; Manufacturing; Markets; Maximization; Memory devices; Optimization; Optimization techniques; Photolithography; Productivity; Profitability; profitability enhancements; Return on investment; Semiconductor device modeling; Throughput; wafer manufacturing strategy; Wafer map optimization; wafer productivity; yield modeling
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2018.2870253

In order to maintain a competitive edge in the face of increasing global competition in the semiconductor memory market, device makers in the IC memory industry need to continuously improve their productivity by implementing novel manufacturing strategies that are applicable to the rapid market changes characteristic of the industry. Conventional wafer productivity strategies typically only focus on maximizing gross die out, a strategy which does not address wafer productivity for profitability, i.e., return on investment (ROI), with respect to current market situations, since ROI is significantly influenced not only by the number of gross die out, but also by other factors both within the manufacturing line, for example by the number of photolithography shots per wafer, and also by external factors, most importantly the market price of the memory devices being produced. In this paper, we propose a novel productivity model based on ROI and use the ROI-based model to evaluate wafer maps and thereby to determine optimal chip sizes for maximizing fab productivity. To evaluate wafer productivity accurately, we predicted yields from various wafer map configurations using deep neural networks, and, to search for productivity-maximal wafer maps in extremely large search spaces, we adopted differential evolution as the optimization technique. Comparison results have demonstrated that our proposed method effectively improved wafer productivity by up to 7.96%, in contrast with the old method. By incorporating these market-oriented indicators into standard yield models, we offer a new way for memory device manufacturers to maximize productivity and maintain competitive advantage for their semiconductor fabrication lines.