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Logic minimization and wide fan‐in issues in DPL‐based cryptocircuits against power analysis attacks
Summary This paper discusses the use of logic minimization techniques and wide fan‐in primitives and how the design and evaluation of combinational blocks for full‐custom dual‐precharge‐logic‐based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for...
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Published in: | International journal of circuit theory and applications 2019-02, Vol.47 (2), p.238-253 |
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Main Authors: | , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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This paper discusses the use of logic minimization techniques and wide fan‐in primitives and how the design and evaluation of combinational blocks for full‐custom dual‐precharge‐logic‐based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate‐level design of substitution boxes, widely used in block ciphers, using sense‐amplifier–based logic in a 90‐nm technology. The security of several proposals was evaluated with simulation‐based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security‐power‐delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power‐efficient.
This paper discusses the use of logic minimization techniques and wide fan‐in primitives and how the design of full‐custom dual precharge logic‐based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed to the gate‐level design using sense‐amplifier–based logic in a 90‐nm technology. The correlation power analysis attacks results showed increased security‐power‐delay figures for our proposals and indicated that those solutions which minimized area occupation were both the most secure and the most power‐efficient. |
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ISSN: | 0098-9886 1097-007X |
DOI: | 10.1002/cta.2587 |