A tamper resistant hardware accelerator for RSA cryptographic applications

• Published in: Journal of systems architecture 2004-12, Vol.50 (12), p.711-727
• Main Authors: Saggese, G.P., Romano, L., Mazzocca, N., Mazzeo, A.
• Format: Article
• Language: English
• Subjects: Algorithms; Computer peripherals; Cybersecurity; Field Programmable Gate Arrays (FPGAs); RSA cryptosystems; Security-and performance-critical applications; Studies
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/j.sysarc.2004.04.002

This paper presents an hardware accelerator which can effectively improve the security and the performance of virtually any RSA cryptographic application. The accelerator integrates two crucial security- and performance-enhancing facilities: an RSA processor and an RSA key-store. An RSA processor is a dedicated hardware block which executes the RSA algorithm. An RSA key-store is a dedicated device for securely storing RSA key-pairs. We chose RSA since it is by far the most widely adopted standard in public key cryptography. We describe the main functional blocks of the hardware accelerator and their interactions, and comment architectural solutions we adopted for maximizing security and performance while minimizing the cost in terms of hardware resources. We then present an FPGA-based implementation of the proposed architecture, which relies on a Commercial Off The Shelf (COTS) programmable hardware board. Finally, we evaluate the system in terms of performance and chip area occupation, and comment the design trade-offs resulting from different levels of parallelism.