Register bypassing in an asynchronous superscalar processor

Register bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with the danger that the advantages of asynchronous operation may be nullified by...

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Bibliographic Details
Published in:Journal of systems architecture 2000-07, Vol.46 (9), p.749-764
Main Authors: Davis, S.J, Elston, C.J, Findlay, P.A
Format: Article
Language:English
Subjects:
Asynchronous
Asynchronous processor simulation
Dual-/multiple-instruction issue
Motherboards
Operand forwarding
Performance evaluation
Register bypassing
Studies
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Summary:Register bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with the danger that the advantages of asynchronous operation may be nullified by reintroducing the lock-step operation of synchronous processors. We present a novel implementation of register bypassing in an asynchronous processor architecture. Our technique of Decoupled Operand Forwarding provides centralized control over the bypassing operation, yet allows multiple execution units to function asynchronously. Our ideas are presented within the context of the development of Hades, a generic asynchronous processor architecture. We employ single-issue and dual-issue simulations of Hades to quantify the benefits of Decoupled Operand Forwarding and conclude that Decoupled Operand Forwarding yields significant speedups because of its success in removing register files from the critical timing path.
ISSN:1383-7621
1873-6165
DOI:10.1016/S1383-7621(99)00029-6