A Phase-Calibration Method for Vector-Sum Phase Shifters Using a Self-Generated LUT

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-04, Vol.66 (4), p.1632-1642
• Main Authors: Kalyoncu, Ilker, Ozeren, Emre, Burak, Abdurrahman, Ceylan, Omer, Gurbuz, Yasar
• Format: Article
• Language: English
• Subjects: Amplification; Amplifiers; Analog to digital conversion; Analog to digital converters; BiCMOS; Calibration; Couplers; Data processing; Errors; Gain; Insertion loss; look-up table; Lookup tables; Mathematical analysis; Phase error; phase shifter calibration; Phase shifters; Phased arrays; Power consumption; Power measurement; process compensation; Radio frequency; Self calibration; SiGe; System-on-chip; Topology; Tuning; Variable gain; vector-sum phase shifter
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2018.2885172

This paper presents a new self-calibration method for vector-sum phase shifters (PS) to compensate for process variations and achieve reconfigurable operating frequency. The calibration system generates a look-up table for the control voltages of the variable-gain amplifiers of the PS to minimize the rms phase error at a frequency of interest. The calibration system consists of a coupled-line coupler, an amplifier, a power detector (PD), an analog-to-digital converter, and a data processing unit. In this calibration method, first, the amplitudes of IQ vectors are swept and their powers are measured. Then, phase errors are calculated from these power measurements using the cosine formula. Finally, the vector pairs providing the least phase error are chosen for each desired phase shift. The practicality of the proposed system is demonstrated by realizing a self-calibrated X -band 7-b PS fabricated in IHP 0.25- \mu \text{m} SiGe BiCMOS technology, including the on-chip coupler, amplifier, and PD. The calibration system improves the rms phase error by at least 1°, does not degrade the rms gain error, and increases the insertion loss by 1.6 dB. The self-calibrated PS achieves a 2° rms phase error across X -band frequencies. The overall chip size is 2.6 mm 2 . The power consumption of the PS and the overall system are 110 and 233 mW, respectively. This built-in calibration system mitigates process variation effects, and the performance of the PS can be optimized for any center frequency across X -band.