An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

• Published in: IEEE journal of solid-state circuits 2019-04, Vol.54 (4), p.1074-1085
• Main Authors: Satpathy, Sudhir K., Mathew, Sanu K., Kumar, Raghavan, Suresh, Vikram, Anders, Mark A., Kaul, Himanshu, Agarwal, Amit, Hsu, Steven, Krishnamurthy, Ram K., De, Vivek
• Format: Article
• Language: English
• Subjects: Arrays; Authentication; Bias; bit error; Calibration; CMOS; Cryptography; Design for recycling; Digital media; Encryption; Energy consumption; Entropy; Entropy (Information theory); entropy source (ES); Error analysis; Extractors; Generators; hamming distance; Hardening; Masking; physically unclonable function (PUF); Post-processing; Protocols; Random numbers; Self calibration; Servers; stability; stress hardening; temporal majority voting (TMV); true random number generators (TRNG); Von Neumann (VN) extraction; Weight reduction
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2886350

This paper describes a unified static/dynamic entropy generator based on a 512-b common entropy source (ES) array fabricated in 14-nm tri-gate CMOS with reconfigurable and adaptive post-processing circuits implemented on Arria 10 FPGA, targeted for flexible and secure privacy preserving mutual authentication on compact trusted mote platforms at the edge of internet of things. Several conditioning techniques that include temporal majority voting (TMV)-assisted ES array segregation with integrated bias tracking, three-way in-line self-calibration for tolerance to process-voltage-temperature variation, tri-level hierarchical Von Neumann (VN) extraction to maximize entropy harvesting, soft-dark bit masking for improving physically unclonable function (PUF) stability, and selective stress hardening to co-optimize the ES array for static-dynamic entropy with bias aware device aging enable simultaneous PUF and true random number generator (TRNG) operation with 1.48 and 0.56 Gb/s throughput, respectively, measured at 650 mV, 70 °C. The all-digital design with a compact layout footprint of 2114 \mu \text{m}^{2} facilitates seamless integration in area constrained system-on-chips while achieving: 1) 25% area savings over conventional separate PUF and TRNG implementations; 2) cryptographic quality TRNG stream that passes all NIST randomness tests with 0.38 average p-value; 3) 1.6\times higher extractor performance at 9\times lower area with 750-gate hierarchical VN circuit over conventional light-weight entropy extractors; 4) 0.9996/0.99997 static/dynamic Shannon entropy indicating unbiased PUF/TRNG streams; 5) ultra-low energy consumption of 2.5 and 0.46 pJ/bit measured at 650 mV, 70 °C in TRNG and PUF modes; 6) 40% higher TRNG throughput with three-way self-calibration featuring coarse-grain column swap, fine-grain incremental ES substitution, and residual entropy recycling; 7) resistance to power injection attacks as measured by 64% higher performance over un-calibrated design in the presence 200-mV supply noise; 8) 2.8% PUF bit-error measured at 0.55-0.75 V, 25 °C-110 °C with 15-way TMV and soft dark-bit masking over a window of 100 cycles; 9) 14.8\times inter and intra-PUF ha