High-speed ultra-compact all-optical NOT and AND logic gates designed by a multi-objective particle swarm optimized method

• Published in: Optics and laser technology 2019-08, Vol.116, p.322-327
• Main Authors: Lu, Qichao, Yan, Xin, Wei, Wei, Zhang, Xia, Zhang, Mingqian, Zheng, Jiahui, Li, Bang, luo, Yanbin, Lin, Qimin, Ren, Xiaomin
• Format: Article
• Language: English
• Subjects: Design; Design optimization; FDTD; Gates; Global optimization; High speed; Integrated circuits; Logic circuits; Logic gates; Multi-objective particle swarm optimization; Multiple objective analysis; Phase transitions; Photonics; Robustness; SOI
• ISSN: 0030-3992; 1879-2545
• DOI: 10.1016/j.optlastec.2019.03.032

•Logic NOT and AND gates with a footprint of 1.2 × 1.2 μm2 is designed.•The respond time of our devices is less than 0.25 ps.•The devices keep functional when pixel side length varies from 112 to 125 nm.•Both gates have good tolerance for Input phase difference. We have designed high-speed ultra-compact all-optical NOT and AND gates operating at 1550 nm on silicon-on-insulator (SOI) by a multi-objetice particle swarm optimized inverse-design method. The two gates have a similar four-port structure based on an extremely small area of 1.2 × 1.2 µm2. The ultra-small size of device leads to a short respond time less than 0.25 ps. Benefiting from the global optimization of our inverse-design method, our devices have a good tolerance on phase changes of input light. The not gate could keep working while the phase difference of input ranges from 0 to 0.3 π. The situation for AND gate is −0.25 to 0.75 π. Also the maximum contrast ratio is 7.16 dB for the NOT gate and 3.98 for the AND gate, respectively. Moreover, we demonstrate that the design method could have tolerance for small changes in device geometry, which means that our logic gates could remain functional while the pixel side length ranges from 112 to 125 nm. The tiny size, fast response and high robustness make our devices promising for future photonic-integrated circuits.