Motor fault detection using Quaternion Signal Analysis on FPGA

•Signal classification based on statistical geometrical approach, using quaternion algebra.•Statistic- geometric model for detecting fault condition in induction motors.•High accuracy signal classification with sampled reduced constraint.•High performance implementation of Quaternion Signal Analysis...

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Bibliographic Details
Published in:Measurement : journal of the International Measurement Confederation 2019-05, Vol.138, p.416-424
Main Authors: Contreras-Hernandez, Jose L., Almanza-Ojeda, Dora L., Ledesma, Sergio, Ibarra-Manzano, Mario A.
Format: Article
Language:English
Subjects:
Accelerometers
Decision trees
Fault detection
Fault diagnosis
Feature extraction
Field programmable gate arrays
FPGA
Hardware description languages
QSA
Quaternions
Real time
Real time processing
Signal analysis
Statistical methods
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Summary:•Signal classification based on statistical geometrical approach, using quaternion algebra.•Statistic- geometric model for detecting fault condition in induction motors.•High accuracy signal classification with sampled reduced constraint.•High performance implementation of Quaternion Signal Analysis on FPGA.•Modular implementation that facilitates the updating and adaptation of each stage in the system. In industry, the maintenance of motors strategy requires accurate monitoring techniques that indicate the motor working conditions and the type of fault detected. In this work, the Quaternion Signal Analysis (QSA) method is used to analyze statistical features of motor signals in order to detect faulty and healthy conditions in motor induction. The use of quaternion arithmetic to rotate and characterize signal behavior in a time domain provides accurate results using a reduced number of samples during classification. The accelerometer and current signals measured from the motor are modeled as quaternions. The decision trees method is used to classify healthy (HLT), unbalanced pulley (BAL) and bearing fault (BRN) motor conditions. The proposed methodology was implemented on an FPGA device through Very-High-Speed Hardware Description Language (VHDL) to validate the effectiveness of our method in real motor working conditions. This architecture was tested to validate the effectiveness in real motor working conditions.
ISSN:0263-2241
1873-412X
DOI:10.1016/j.measurement.2019.01.088