Architecture and analysis of a dynamically-scheduled real-time memory controller

• Published in: Real-time systems 2016-09, Vol.52 (5), p.675-729
• Main Authors: Li, Yonghui, Akesson, Benny, Goossens, Kees
• Format: Article
• Language: English
• Subjects: Algorithms; Communications Engineering; Computer Science; Computer Systems Organization and Communication Networks; Control; Control systems design; Controllers; Embedded systems; Mechatronics; Networks; Performance and Reliability; Real time; Response time; Response time (computers); Robotics; Scheduling; Special Purpose and Application-Based Systems
• ISSN: 0922-6443; 1573-1383
• DOI: 10.1007/s11241-015-9235-y

Memory controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a memory controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed memory controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.