Toward Increasing the Difficulty of Reverse Engineering of RSFQ Circuits

Integrated circuit (IC) camouflaging is a defense to defeat image-based reverse engineering. The security of CMOS ICs has been extensively studied and camouflage techniques have been developed. A camouflaging method is introduced here to protect superconducting electronics, specifically, rapid singl...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2020-04, Vol.30 (3), p.1-13
Main Authors: Kumar, Harshit, Jabbari, Tahereh, Krylov, Gleb, Basu, Kanad, Friedman, Eby G., Karri, Ramesh
Format: Article
Language:English
Subjects:
Benchmarks
Camouflage
Camouflaging
Clocks
CMOS
CMOS technology
hardware security
Integrated circuits
Josephson junctions
Logic gates
Microprocessors
rapid single flux quantum (RSFQ)
Reverse engineering
superconducting electronics
Temporal distribution
Watermarking
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Summary:Integrated circuit (IC) camouflaging is a defense to defeat image-based reverse engineering. The security of CMOS ICs has been extensively studied and camouflage techniques have been developed. A camouflaging method is introduced here to protect superconducting electronics, specifically, rapid single flux quantum (RSFQ) technology, from reverse engineering. RSFQ camouflaged units have been developed by applying the structural similarity of RSFQ standard cells. A defense using camouflaged RSFQ cells combined with obfuscating the temporal distribution of inputs to the IC increases the attacker's effort to decamouflage. The approach establishes the complexity class of RSFQ decamouflaging and a model checker is applied to evaluate the strength of the defenses. These techniques have been evaluated on ISCAS'85 combinational benchmarks and the controllers of the OpenSPARC T1 microprocessor. A dummy Josephson junction fabrication process adds two additional mask steps that increase the cost overhead. Camouflaging 100% of the benchmark circuits results in an area and power overhead of almost 40%. In the case of the OpenSPARC processor, the approach requires near-zero area, power, and performance overhead even when 100% of the sensitive parts of the processor are camouflaged.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2019.2901895