A Highly Linear Neuromorphic Synaptic Device Based on Regulated Charge Trap/Detrap

In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated co...

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Bibliographic Details
Published in:IEEE electron device letters 2019-11, Vol.40 (11), p.1848-1851
Main Authors: Choi, Jong-Moon, Park, Eun-Je, Woo, Je-Joong, Kwon, Kee-Won
Format: Article
Language:English
Subjects:
Capacitance
charge trap
Circuits
CMOS
CMOS-compatible
Erbium
floating gate
incremental step pulse programming (ISPP)
linear programming
Linearity
Neuromorphics
Nonvolatile memory
Programming
Real time
synaptic device
Tunneling
Weight
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Summary:In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated column write driver for embedded incremental step pulse programming (ISPP) via analog feedback. Utilizing real-time ISPP, the linearity and symmetry of the weight update were significantly improved due to the content-aware programming strength. Moreover, the proposed circuit technique provides flexibility regarding the size of the program/erase steps in addition to the superior linearity. The proposed FG cells with peripheral circuits are fabricated using 180nm CMOS technology and exhibited a differential non-linearity (DNL) less than 0.946 least significant bit (LSB) with 100 weight states. The excellent linearity remains unchanged even when the directions of potentiation /depression are reversed throughout the entire range.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2019.2943113